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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Gowin Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>v1.8.0.02Beta</td>
</tr>
<tr>
<td class="label">Series, Device, Package, Speed, Operating Conditions</td>
<td>GW1N, GW1N-4, LQFP144, 6, COMMERCIAL</td>
</tr>
<tr>
<td class="label">Design Name</td>
<td>SSD1306</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\fpga_oled_ssd1306\impl\synthesize\rev_1\oled_ssd1306.vm</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Timing Report File</td>
<td>C:\fpga_oled_ssd1306\impl\pnr\oled_ssd1306.tr.html</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Oct 09 11:02:40 2018
</td>
</tr>
<tr>
<td class="label">Command Line</td>
<td>C:\Gowin\1.8\Pnr\bin\gowin.exe -do C:\fpga_oled_ssd1306\impl\pnr\cmd.do </td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2017 Gowin Semiconductor Corporation.                      All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 1.14V 85C</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.26V 0C</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>311</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>240</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>DEFAULT_CLK</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Fmax</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>DEFAULT_CLK</td>
<td>127.841(MHz)</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>DEFAULT_CLK</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>DEFAULT_CLK</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>2.178</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[6]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.222</td>
</tr>
<tr>
<td>2</td>
<td>2.586</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[16]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.814</td>
</tr>
<tr>
<td>3</td>
<td>2.600</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[19]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.800</td>
</tr>
<tr>
<td>4</td>
<td>2.653</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[20]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.747</td>
</tr>
<tr>
<td>5</td>
<td>2.653</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[21]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.747</td>
</tr>
<tr>
<td>6</td>
<td>2.653</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[18]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.747</td>
</tr>
<tr>
<td>7</td>
<td>2.685</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[12]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.715</td>
</tr>
<tr>
<td>8</td>
<td>2.685</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[11]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.715</td>
</tr>
<tr>
<td>9</td>
<td>2.995</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[13]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.405</td>
</tr>
<tr>
<td>10</td>
<td>2.995</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[14]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.405</td>
</tr>
<tr>
<td>11</td>
<td>2.995</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[24]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.405</td>
</tr>
<tr>
<td>12</td>
<td>3.096</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[22]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.304</td>
</tr>
<tr>
<td>13</td>
<td>3.721</td>
<td>cnt_Z[5]/Q</td>
<td>clk_ssd1306_0_Z/CE</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.035</td>
</tr>
<tr>
<td>14</td>
<td>5.280</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[23]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.120</td>
</tr>
<tr>
<td>15</td>
<td>5.622</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[17]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.778</td>
</tr>
<tr>
<td>16</td>
<td>5.736</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[15]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.664</td>
</tr>
<tr>
<td>17</td>
<td>6.021</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[10]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.379</td>
</tr>
<tr>
<td>18</td>
<td>6.078</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[9]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.322</td>
</tr>
<tr>
<td>19</td>
<td>6.135</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[8]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.265</td>
</tr>
<tr>
<td>20</td>
<td>6.192</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[7]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.208</td>
</tr>
<tr>
<td>21</td>
<td>6.824</td>
<td>cnt_Z[1]/Q</td>
<td>cnt_Z[5]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.576</td>
</tr>
<tr>
<td>22</td>
<td>6.881</td>
<td>cnt_Z[1]/Q</td>
<td>cnt_Z[4]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.519</td>
</tr>
<tr>
<td>23</td>
<td>6.938</td>
<td>cnt_Z[1]/Q</td>
<td>cnt_Z[3]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.462</td>
</tr>
<tr>
<td>24</td>
<td>6.995</td>
<td>cnt_Z[1]/Q</td>
<td>cnt_Z[2]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.405</td>
</tr>
<tr>
<td>25</td>
<td>7.325</td>
<td>cnt_Z[0]/Q</td>
<td>cnt_Z[1]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.075</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.708</td>
<td>clk_ssd1306_0_Z/Q</td>
<td>clk_ssd1306_0_Z/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>2</td>
<td>0.853</td>
<td>cnt_Z[2]/Q</td>
<td>cnt_Z[2]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.853</td>
</tr>
<tr>
<td>3</td>
<td>0.853</td>
<td>cnt_Z[0]/Q</td>
<td>cnt_Z[0]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.853</td>
</tr>
<tr>
<td>4</td>
<td>0.853</td>
<td>cnt_Z[8]/Q</td>
<td>cnt_Z[8]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.853</td>
</tr>
<tr>
<td>5</td>
<td>1.085</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[5]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.085</td>
</tr>
<tr>
<td>6</td>
<td>1.085</td>
<td>cnt_Z[4]/Q</td>
<td>cnt_Z[4]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.085</td>
</tr>
<tr>
<td>7</td>
<td>1.085</td>
<td>cnt_Z[10]/Q</td>
<td>cnt_Z[10]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.085</td>
</tr>
<tr>
<td>8</td>
<td>1.088</td>
<td>cnt_Z[1]/Q</td>
<td>cnt_Z[1]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.088</td>
</tr>
<tr>
<td>9</td>
<td>1.088</td>
<td>cnt_Z[9]/Q</td>
<td>cnt_Z[9]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.088</td>
</tr>
<tr>
<td>10</td>
<td>1.088</td>
<td>cnt_Z[23]/Q</td>
<td>cnt_Z[23]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.088</td>
</tr>
<tr>
<td>11</td>
<td>1.093</td>
<td>cnt_Z[7]/Q</td>
<td>cnt_Z[7]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.093</td>
</tr>
<tr>
<td>12</td>
<td>1.093</td>
<td>cnt_Z[15]/Q</td>
<td>cnt_Z[15]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.093</td>
</tr>
<tr>
<td>13</td>
<td>1.093</td>
<td>cnt_Z[3]/Q</td>
<td>cnt_Z[3]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.093</td>
</tr>
<tr>
<td>14</td>
<td>1.422</td>
<td>cnt_Z[17]/Q</td>
<td>cnt_Z[17]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.422</td>
</tr>
<tr>
<td>15</td>
<td>1.693</td>
<td>cnt_Z[21]/Q</td>
<td>cnt_Z[21]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.693</td>
</tr>
<tr>
<td>16</td>
<td>1.813</td>
<td>cnt_Z[24]/Q</td>
<td>cnt_Z[24]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.813</td>
</tr>
<tr>
<td>17</td>
<td>1.833</td>
<td>cnt_Z[23]/Q</td>
<td>clk_ssd1306_0_Z/CE</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.848</td>
</tr>
<tr>
<td>18</td>
<td>1.873</td>
<td>cnt_Z[20]/Q</td>
<td>cnt_Z[20]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.873</td>
</tr>
<tr>
<td>19</td>
<td>1.873</td>
<td>cnt_Z[22]/Q</td>
<td>cnt_Z[22]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.873</td>
</tr>
<tr>
<td>20</td>
<td>1.988</td>
<td>cnt_Z[23]/Q</td>
<td>cnt_Z[13]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.988</td>
</tr>
<tr>
<td>21</td>
<td>1.988</td>
<td>cnt_Z[23]/Q</td>
<td>cnt_Z[14]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.988</td>
</tr>
<tr>
<td>22</td>
<td>2.075</td>
<td>cnt_Z[19]/Q</td>
<td>cnt_Z[19]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.075</td>
</tr>
<tr>
<td>23</td>
<td>2.290</td>
<td>cnt_Z[23]/Q</td>
<td>cnt_Z[12]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.290</td>
</tr>
<tr>
<td>24</td>
<td>2.290</td>
<td>cnt_Z[23]/Q</td>
<td>cnt_Z[11]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.290</td>
</tr>
<tr>
<td>25</td>
<td>2.298</td>
<td>cnt_Z[23]/Q</td>
<td>cnt_Z[16]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>2.298</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[21]</td>
</tr>
<tr>
<td>2</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td>3</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[16]</td>
</tr>
<tr>
<td>4</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[9]</td>
</tr>
<tr>
<td>5</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[8]</td>
</tr>
<tr>
<td>6</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[15]</td>
</tr>
<tr>
<td>7</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[7]</td>
</tr>
<tr>
<td>8</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>clk_ssd1306_0_Z</td>
</tr>
<tr>
<td>9</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td>10</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[5]</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.178</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.592</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.227</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>10.560</td>
<td>1.333</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C14[0][A]</td>
<td>cnt_3_cZ[6]/I1</td>
</tr>
<tr>
<td>11.592</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C14[0][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[6]/F</td>
</tr>
<tr>
<td>11.592</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C14[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[6]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C14[0][A]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C14[0][A]</td>
<td>cnt_Z[6]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.788, 52.449%; route: 2.976, 41.204%; tC2Q: 0.458, 6.346%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.586</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.184</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[16]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.227</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>10.085</td>
<td>0.857</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[2][B]</td>
<td>cnt_3_cZ[16]/I1</td>
</tr>
<tr>
<td>11.184</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C12[2][B]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[16]/F</td>
</tr>
<tr>
<td>11.184</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[16]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[2][B]</td>
<td>cnt_Z[16]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[16]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C12[2][B]</td>
<td>cnt_Z[16]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.855, 56.577%; route: 2.500, 36.697%; tC2Q: 0.458, 6.727%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.600</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.170</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.227</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>10.071</td>
<td>0.843</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[0][B]</td>
<td>cnt_3_cZ[19]/I1</td>
</tr>
<tr>
<td>11.170</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C12[0][B]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[19]/F</td>
</tr>
<tr>
<td>11.170</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[19]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[0][B]</td>
<td>cnt_Z[19]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C12[0][B]</td>
<td>cnt_Z[19]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.855, 56.690%; route: 2.487, 36.569%; tC2Q: 0.458, 6.740%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.653</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.117</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[20]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.227</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>10.085</td>
<td>0.857</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[1][A]</td>
<td>cnt_3_cZ[20]/I1</td>
</tr>
<tr>
<td>11.117</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C12[1][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[20]/F</td>
</tr>
<tr>
<td>11.117</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[20]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[1][A]</td>
<td>cnt_Z[20]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[20]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C12[1][A]</td>
<td>cnt_Z[20]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.788, 56.146%; route: 2.500, 37.061%; tC2Q: 0.458, 6.793%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.653</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.117</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[21]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.227</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>10.085</td>
<td>0.857</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[1][B]</td>
<td>cnt_3_cZ[21]/I1</td>
</tr>
<tr>
<td>11.117</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C12[1][B]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[21]/F</td>
</tr>
<tr>
<td>11.117</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[21]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[1][B]</td>
<td>cnt_Z[21]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[21]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C12[1][B]</td>
<td>cnt_Z[21]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.788, 56.146%; route: 2.500, 37.061%; tC2Q: 0.458, 6.793%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.653</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.117</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[18]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.227</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>10.085</td>
<td>0.857</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[0][A]</td>
<td>cnt_3_cZ[18]/I1</td>
</tr>
<tr>
<td>11.117</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C12[0][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[18]/F</td>
</tr>
<tr>
<td>11.117</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[18]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[0][A]</td>
<td>cnt_Z[18]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[18]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C12[0][A]</td>
<td>cnt_Z[18]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.788, 56.146%; route: 2.500, 37.061%; tC2Q: 0.458, 6.793%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.685</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.085</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[12]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.227</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>10.053</td>
<td>0.825</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C13[0][B]</td>
<td>cnt_3_cZ[12]/I1</td>
</tr>
<tr>
<td>11.085</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C13[0][B]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[12]/F</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C13[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[12]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C13[0][B]</td>
<td>cnt_Z[12]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[12]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C13[0][B]</td>
<td>cnt_Z[12]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.788, 56.411%; route: 2.469, 36.764%; tC2Q: 0.458, 6.825%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.685</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.085</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[11]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.227</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>10.053</td>
<td>0.825</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C13[0][A]</td>
<td>cnt_3_cZ[11]/I1</td>
</tr>
<tr>
<td>11.085</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C13[0][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[11]/F</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[11]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C13[0][A]</td>
<td>cnt_Z[11]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[11]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C13[0][A]</td>
<td>cnt_Z[11]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.788, 56.411%; route: 2.469, 36.764%; tC2Q: 0.458, 6.825%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.995</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.775</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[13]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.227</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>9.743</td>
<td>0.516</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C13[1][A]</td>
<td>cnt_3_cZ[13]/I1</td>
</tr>
<tr>
<td>10.775</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C13[1][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[13]/F</td>
</tr>
<tr>
<td>10.775</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C13[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[13]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[1][A]</td>
<td>cnt_Z[13]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[13]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C13[1][A]</td>
<td>cnt_Z[13]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.788, 59.139%; route: 2.159, 33.706%; tC2Q: 0.458, 7.156%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.995</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.775</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[14]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.227</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>9.743</td>
<td>0.516</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C13[2][A]</td>
<td>cnt_3_cZ[14]/I1</td>
</tr>
<tr>
<td>10.775</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C13[2][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[14]/F</td>
</tr>
<tr>
<td>10.775</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C13[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[14]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[2][A]</td>
<td>cnt_Z[14]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[14]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C13[2][A]</td>
<td>cnt_Z[14]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.788, 59.139%; route: 2.159, 33.706%; tC2Q: 0.458, 7.156%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.995</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.775</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.227</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>9.743</td>
<td>0.516</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C13[2][B]</td>
<td>cnt_3_cZ[24]/I1</td>
</tr>
<tr>
<td>10.775</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C13[2][B]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[24]/F</td>
</tr>
<tr>
<td>10.775</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C13[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[24]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[2][B]</td>
<td>cnt_Z[24]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C13[2][B]</td>
<td>cnt_Z[24]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.788, 59.139%; route: 2.159, 33.706%; tC2Q: 0.458, 7.156%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.096</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.674</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[22]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.227</td>
<td>1.032</td>
<td>tINS</td>
<td>RF</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>10.048</td>
<td>0.821</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C12[0][A]</td>
<td>cnt_3_cZ[22]/I1</td>
</tr>
<tr>
<td>10.674</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R14C12[0][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[22]/F</td>
</tr>
<tr>
<td>10.674</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[22]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C12[0][A]</td>
<td>cnt_Z[22]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[22]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R14C12[0][A]</td>
<td>cnt_Z[22]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.382, 53.645%; route: 2.464, 39.085%; tC2Q: 0.458, 7.270%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.721</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.405</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.126</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_ssd1306_0_Z</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>5.248</td>
<td>0.420</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td>clk_ssd13063_13_cZ/I3</td>
</tr>
<tr>
<td>6.347</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[3][A]</td>
<td style=" background: #97FFFF;">clk_ssd13063_13_cZ/F</td>
</tr>
<tr>
<td>7.152</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td>clk_ssd13063_22_cZ/I0</td>
</tr>
<tr>
<td>7.777</td>
<td>0.625</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C12[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_22_cZ/F</td>
</tr>
<tr>
<td>8.195</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I2</td>
</tr>
<tr>
<td>9.221</td>
<td>1.026</td>
<td>tINS</td>
<td>RR</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>10.405</td>
<td>1.184</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C14[0][A]</td>
<td style=" font-weight:bold;">clk_ssd1306_0_Z/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C14[0][A]</td>
<td>clk_ssd1306_0_Z/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>clk_ssd1306_0_Z</td>
</tr>
<tr>
<td>14.126</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C14[0][A]</td>
<td>clk_ssd1306_0_Z</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.750, 45.564%; route: 2.827, 46.842%; tC2Q: 0.458, 7.594%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.280</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.490</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C14[0][A]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R12C14[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>5.970</td>
<td>1.142</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.015</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.015</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.072</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.072</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.129</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.129</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.186</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.186</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>7.243</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/COUT</td>
</tr>
<tr>
<td>7.243</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[0][A]</td>
<td>un3_cnt_cry_11_0/CIN</td>
</tr>
<tr>
<td>7.300</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_11_0/COUT</td>
</tr>
<tr>
<td>7.300</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[0][B]</td>
<td>un3_cnt_cry_12_0/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_12_0/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[1][A]</td>
<td>un3_cnt_cry_13_0/CIN</td>
</tr>
<tr>
<td>7.414</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_13_0/COUT</td>
</tr>
<tr>
<td>7.414</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[1][B]</td>
<td>un3_cnt_cry_14_0/CIN</td>
</tr>
<tr>
<td>7.471</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_14_0/COUT</td>
</tr>
<tr>
<td>7.471</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[2][A]</td>
<td>un3_cnt_cry_15_0/CIN</td>
</tr>
<tr>
<td>7.528</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_15_0/COUT</td>
</tr>
<tr>
<td>7.528</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[2][B]</td>
<td>un3_cnt_cry_16_0/CIN</td>
</tr>
<tr>
<td>7.585</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_16_0/COUT</td>
</tr>
<tr>
<td>7.585</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C12[0][A]</td>
<td>un3_cnt_cry_17_0/CIN</td>
</tr>
<tr>
<td>7.642</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C12[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_17_0/COUT</td>
</tr>
<tr>
<td>7.642</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C12[0][B]</td>
<td>un3_cnt_cry_18_0/CIN</td>
</tr>
<tr>
<td>7.699</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C12[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_18_0/COUT</td>
</tr>
<tr>
<td>7.699</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C12[1][A]</td>
<td>un3_cnt_cry_19_0/CIN</td>
</tr>
<tr>
<td>7.756</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C12[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_19_0/COUT</td>
</tr>
<tr>
<td>7.756</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C12[1][B]</td>
<td>un3_cnt_cry_20_0/CIN</td>
</tr>
<tr>
<td>7.813</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C12[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_20_0/COUT</td>
</tr>
<tr>
<td>7.813</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C12[2][A]</td>
<td>un3_cnt_cry_21_0/CIN</td>
</tr>
<tr>
<td>7.870</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C12[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_21_0/COUT</td>
</tr>
<tr>
<td>7.870</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C12[2][B]</td>
<td>un3_cnt_cry_22_0/CIN</td>
</tr>
<tr>
<td>7.927</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C12[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_22_0/COUT</td>
</tr>
<tr>
<td>7.927</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C13[0][A]</td>
<td>un3_cnt_cry_23_0/CIN</td>
</tr>
<tr>
<td>8.490</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_23_0/SUM</td>
</tr>
<tr>
<td>8.490</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C13[0][A]</td>
<td>cnt_Z[23]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.520, 61.162%; route: 1.142, 27.714%; tC2Q: 0.458, 11.124%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.622</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.148</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C14[0][A]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R12C14[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>5.970</td>
<td>1.142</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.015</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.015</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.072</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.072</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.129</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.129</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.186</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.186</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>7.243</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/COUT</td>
</tr>
<tr>
<td>7.243</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[0][A]</td>
<td>un3_cnt_cry_11_0/CIN</td>
</tr>
<tr>
<td>7.300</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_11_0/COUT</td>
</tr>
<tr>
<td>7.300</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[0][B]</td>
<td>un3_cnt_cry_12_0/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_12_0/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[1][A]</td>
<td>un3_cnt_cry_13_0/CIN</td>
</tr>
<tr>
<td>7.414</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_13_0/COUT</td>
</tr>
<tr>
<td>7.414</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[1][B]</td>
<td>un3_cnt_cry_14_0/CIN</td>
</tr>
<tr>
<td>7.471</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_14_0/COUT</td>
</tr>
<tr>
<td>7.471</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[2][A]</td>
<td>un3_cnt_cry_15_0/CIN</td>
</tr>
<tr>
<td>7.528</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_15_0/COUT</td>
</tr>
<tr>
<td>7.528</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[2][B]</td>
<td>un3_cnt_cry_16_0/CIN</td>
</tr>
<tr>
<td>7.585</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_16_0/COUT</td>
</tr>
<tr>
<td>7.585</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C12[0][A]</td>
<td>un3_cnt_cry_17_0/CIN</td>
</tr>
<tr>
<td>8.148</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C12[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_17_0/SUM</td>
</tr>
<tr>
<td>8.148</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[17]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C12[0][A]</td>
<td>cnt_Z[17]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C12[0][A]</td>
<td>cnt_Z[17]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>12</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.178, 57.647%; route: 1.142, 30.222%; tC2Q: 0.458, 12.131%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.736</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.034</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[15]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C14[0][A]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R12C14[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>5.970</td>
<td>1.142</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.015</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.015</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.072</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.072</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.129</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.129</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.186</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.186</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>7.243</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/COUT</td>
</tr>
<tr>
<td>7.243</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[0][A]</td>
<td>un3_cnt_cry_11_0/CIN</td>
</tr>
<tr>
<td>7.300</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_11_0/COUT</td>
</tr>
<tr>
<td>7.300</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[0][B]</td>
<td>un3_cnt_cry_12_0/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_12_0/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[1][A]</td>
<td>un3_cnt_cry_13_0/CIN</td>
</tr>
<tr>
<td>7.414</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_13_0/COUT</td>
</tr>
<tr>
<td>7.414</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[1][B]</td>
<td>un3_cnt_cry_14_0/CIN</td>
</tr>
<tr>
<td>7.471</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_14_0/COUT</td>
</tr>
<tr>
<td>7.471</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C11[2][A]</td>
<td>un3_cnt_cry_15_0/CIN</td>
</tr>
<tr>
<td>8.034</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C11[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_15_0/SUM</td>
</tr>
<tr>
<td>8.034</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C11[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[15]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[2][A]</td>
<td>cnt_Z[15]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[15]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C11[2][A]</td>
<td>cnt_Z[15]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.064, 56.329%; route: 1.142, 31.163%; tC2Q: 0.458, 12.508%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.021</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.749</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[10]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C14[0][A]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R12C14[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>5.970</td>
<td>1.142</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.015</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.015</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.072</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.072</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.129</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.129</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.186</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.186</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>7.749</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/SUM</td>
</tr>
<tr>
<td>7.749</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[10]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[2][B]</td>
<td>cnt_Z[10]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[10]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C10[2][B]</td>
<td>cnt_Z[10]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.779, 52.646%; route: 1.142, 33.791%; tC2Q: 0.458, 13.563%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.078</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.692</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[9]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C14[0][A]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R12C14[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>5.970</td>
<td>1.142</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.015</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.015</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.072</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.072</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.129</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.129</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.692</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/SUM</td>
</tr>
<tr>
<td>7.692</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[9]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[2][A]</td>
<td>cnt_Z[9]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[9]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C10[2][A]</td>
<td>cnt_Z[9]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.722, 51.833%; route: 1.142, 34.371%; tC2Q: 0.458, 13.796%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.135</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.635</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[8]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C14[0][A]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R12C14[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>5.970</td>
<td>1.142</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.015</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.015</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.072</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.072</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.635</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/SUM</td>
</tr>
<tr>
<td>7.635</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[8]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[1][B]</td>
<td>cnt_Z[8]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[8]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C10[1][B]</td>
<td>cnt_Z[8]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.665, 50.992%; route: 1.142, 34.971%; tC2Q: 0.458, 14.037%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.192</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.578</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[7]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C14[0][A]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R12C14[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>5.970</td>
<td>1.142</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.015</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.015</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.578</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/SUM</td>
</tr>
<tr>
<td>7.578</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[7]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td>cnt_Z[7]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[7]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C10[1][A]</td>
<td>cnt_Z[7]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.608, 50.122%; route: 1.142, 35.592%; tC2Q: 0.458, 14.286%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.824</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.946</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R13C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>6.212</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/COUT</td>
</tr>
<tr>
<td>6.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[1][B]</td>
<td>un3_cnt_cry_2_0/CIN</td>
</tr>
<tr>
<td>6.269</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/COUT</td>
</tr>
<tr>
<td>6.269</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[2][A]</td>
<td>un3_cnt_cry_3_0/CIN</td>
</tr>
<tr>
<td>6.326</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/COUT</td>
</tr>
<tr>
<td>6.326</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[2][B]</td>
<td>un3_cnt_cry_4_0/CIN</td>
</tr>
<tr>
<td>6.383</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_4_0/COUT</td>
</tr>
<tr>
<td>6.383</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td>un3_cnt_cry_5_0/CIN</td>
</tr>
<tr>
<td>6.946</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_5_0/SUM</td>
</tr>
<tr>
<td>6.946</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.779, 69.051%; route: 0.339, 13.158%; tC2Q: 0.458, 17.790%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.881</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.889</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[4]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R13C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>6.212</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/COUT</td>
</tr>
<tr>
<td>6.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[1][B]</td>
<td>un3_cnt_cry_2_0/CIN</td>
</tr>
<tr>
<td>6.269</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/COUT</td>
</tr>
<tr>
<td>6.269</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[2][A]</td>
<td>un3_cnt_cry_3_0/CIN</td>
</tr>
<tr>
<td>6.326</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/COUT</td>
</tr>
<tr>
<td>6.326</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[2][B]</td>
<td>un3_cnt_cry_4_0/CIN</td>
</tr>
<tr>
<td>6.889</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_4_0/SUM</td>
</tr>
<tr>
<td>6.889</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C9[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[4]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[2][B]</td>
<td>cnt_Z[4]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[4]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C9[2][B]</td>
<td>cnt_Z[4]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.722, 68.351%; route: 0.339, 13.456%; tC2Q: 0.458, 18.193%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.938</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.832</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R13C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>6.212</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/COUT</td>
</tr>
<tr>
<td>6.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[1][B]</td>
<td>un3_cnt_cry_2_0/CIN</td>
</tr>
<tr>
<td>6.269</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/COUT</td>
</tr>
<tr>
<td>6.269</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[2][A]</td>
<td>un3_cnt_cry_3_0/CIN</td>
</tr>
<tr>
<td>6.832</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/SUM</td>
</tr>
<tr>
<td>6.832</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C9[2][A]</td>
<td>cnt_Z[3]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.665, 67.619%; route: 0.339, 13.768%; tC2Q: 0.458, 18.614%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.995</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.775</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R13C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>6.212</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/COUT</td>
</tr>
<tr>
<td>6.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[1][B]</td>
<td>un3_cnt_cry_2_0/CIN</td>
</tr>
<tr>
<td>6.775</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/SUM</td>
</tr>
<tr>
<td>6.775</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[2]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][B]</td>
<td>cnt_Z[2]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[2]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C9[1][B]</td>
<td>cnt_Z[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.608, 66.851%; route: 0.339, 14.094%; tC2Q: 0.458, 19.055%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>7.325</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.444</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[0]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[0][B]</td>
<td>cnt_Z[0]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R13C9[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[0]/Q</td>
</tr>
<tr>
<td>4.836</td>
<td>0.008</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[0][B]</td>
<td>un3_cnt_cry_0_0/I0</td>
</tr>
<tr>
<td>5.881</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_0_0/COUT</td>
</tr>
<tr>
<td>5.881</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[1][A]</td>
<td>un3_cnt_cry_1_0/CIN</td>
</tr>
<tr>
<td>6.444</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/SUM</td>
</tr>
<tr>
<td>6.444</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C9[1][A]</td>
<td>cnt_Z[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.608, 77.512%; route: 0.008, 0.395%; tC2Q: 0.458, 22.093%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.067</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_ssd1306_0_Z</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_ssd1306_0_Z</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C14[0][A]</td>
<td>clk_ssd1306_0_Z/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>74</td>
<td>R13C14[0][A]</td>
<td style=" font-weight:bold;">clk_ssd1306_0_Z/Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C14[0][A]</td>
<td>clk_ssd1306_i_i_cZ/I0</td>
</tr>
<tr>
<td>4.067</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C14[0][A]</td>
<td style=" background: #97FFFF;">clk_ssd1306_i_i_cZ/F</td>
</tr>
<tr>
<td>4.067</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C14[0][A]</td>
<td style=" font-weight:bold;">clk_ssd1306_0_Z/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C14[0][A]</td>
<td>clk_ssd1306_0_Z/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>clk_ssd1306_0_Z</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C14[0][A]</td>
<td>clk_ssd1306_0_Z</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.853</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.212</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[2]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][B]</td>
<td>cnt_Z[2]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C9[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[2]/Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C9[1][B]</td>
<td>un3_cnt_cry_2_0/I0</td>
</tr>
<tr>
<td>4.212</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/SUM</td>
</tr>
<tr>
<td>4.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[2]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][B]</td>
<td>cnt_Z[2]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[2]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C9[1][B]</td>
<td>cnt_Z[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.853</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.212</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[0]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[0][B]</td>
<td>cnt_Z[0]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C9[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[0]/Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C9[0][B]</td>
<td>un3_cnt_cry_0_0/I0</td>
</tr>
<tr>
<td>4.212</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_0_0/SUM</td>
</tr>
<tr>
<td>4.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C9[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[0]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[0][B]</td>
<td>cnt_Z[0]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[0]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C9[0][B]</td>
<td>cnt_Z[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.853</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.212</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[8]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[8]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[1][B]</td>
<td>cnt_Z[8]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[8]/Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C10[1][B]</td>
<td>un3_cnt_cry_8_0/I0</td>
</tr>
<tr>
<td>4.212</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/SUM</td>
</tr>
<tr>
<td>4.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[8]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[1][B]</td>
<td>cnt_Z[8]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[8]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C10[1][B]</td>
<td>cnt_Z[8]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.085</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.444</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[0][A]</td>
<td>un3_cnt_cry_5_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_5_0/SUM</td>
</tr>
<tr>
<td>4.444</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>cnt_Z[5]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.658%; route: 0.234, 21.615%; tC2Q: 0.333, 30.727%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.085</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.444</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[4]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[4]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[2][B]</td>
<td>cnt_Z[4]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R13C9[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[4]/Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C9[2][B]</td>
<td>un3_cnt_cry_4_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C9[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_4_0/SUM</td>
</tr>
<tr>
<td>4.444</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C9[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[4]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[2][B]</td>
<td>cnt_Z[4]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[4]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C9[2][B]</td>
<td>cnt_Z[4]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.658%; route: 0.234, 21.615%; tC2Q: 0.333, 30.727%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.085</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.444</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[10]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[10]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[2][B]</td>
<td>cnt_Z[10]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R13C10[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[10]/Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C10[2][B]</td>
<td>un3_cnt_cry_10_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/SUM</td>
</tr>
<tr>
<td>4.444</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[10]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[2][B]</td>
<td>cnt_Z[10]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[10]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C10[2][B]</td>
<td>cnt_Z[10]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.658%; route: 0.234, 21.615%; tC2Q: 0.333, 30.727%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.088</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.447</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/Q</td>
</tr>
<tr>
<td>3.930</td>
<td>0.238</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C9[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>4.447</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/SUM</td>
</tr>
<tr>
<td>4.447</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C9[1][A]</td>
<td>cnt_Z[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.088</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.447</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[9]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[9]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[2][A]</td>
<td>cnt_Z[9]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[9]/Q</td>
</tr>
<tr>
<td>3.930</td>
<td>0.238</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C10[2][A]</td>
<td>un3_cnt_cry_9_0/I0</td>
</tr>
<tr>
<td>4.447</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/SUM</td>
</tr>
<tr>
<td>4.447</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C10[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[9]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[2][A]</td>
<td>cnt_Z[9]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[9]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C10[2][A]</td>
<td>cnt_Z[9]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.088</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.447</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/Q</td>
</tr>
<tr>
<td>3.930</td>
<td>0.238</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C13[0][A]</td>
<td>un3_cnt_cry_23_0/I0</td>
</tr>
<tr>
<td>4.447</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_23_0/SUM</td>
</tr>
<tr>
<td>4.447</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C13[0][A]</td>
<td>cnt_Z[23]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.093</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.452</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[7]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[7]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td>cnt_Z[7]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C10[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[7]/Q</td>
</tr>
<tr>
<td>3.935</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C10[1][A]</td>
<td>un3_cnt_cry_7_0/I0</td>
</tr>
<tr>
<td>4.452</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/SUM</td>
</tr>
<tr>
<td>4.452</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[7]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td>cnt_Z[7]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[7]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C10[1][A]</td>
<td>cnt_Z[7]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.304%; route: 0.243, 22.197%; tC2Q: 0.333, 30.499%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.093</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.452</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[15]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[15]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[2][A]</td>
<td>cnt_Z[15]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C11[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[15]/Q</td>
</tr>
<tr>
<td>3.935</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C11[2][A]</td>
<td>un3_cnt_cry_15_0/I0</td>
</tr>
<tr>
<td>4.452</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C11[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_15_0/SUM</td>
</tr>
<tr>
<td>4.452</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C11[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[15]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[2][A]</td>
<td>cnt_Z[15]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[15]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C11[2][A]</td>
<td>cnt_Z[15]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.304%; route: 0.243, 22.197%; tC2Q: 0.333, 30.499%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.093</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.452</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/Q</td>
</tr>
<tr>
<td>3.935</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C9[2][A]</td>
<td>un3_cnt_cry_3_0/I0</td>
</tr>
<tr>
<td>4.452</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C9[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/SUM</td>
</tr>
<tr>
<td>4.452</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C9[2][A]</td>
<td>cnt_Z[3]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.304%; route: 0.243, 22.197%; tC2Q: 0.333, 30.499%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.422</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.781</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C12[0][A]</td>
<td>cnt_Z[17]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[17]/Q</td>
</tr>
<tr>
<td>4.264</td>
<td>0.572</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C12[0][A]</td>
<td>un3_cnt_cry_17_0/I0</td>
</tr>
<tr>
<td>4.781</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C12[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_17_0/SUM</td>
</tr>
<tr>
<td>4.781</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[17]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C12[0][A]</td>
<td>cnt_Z[17]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C12[0][A]</td>
<td>cnt_Z[17]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 36.360%; route: 0.572, 40.198%; tC2Q: 0.333, 23.443%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.693</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.052</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[21]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[21]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[1][B]</td>
<td>cnt_Z[21]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R12C12[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[21]/Q</td>
</tr>
<tr>
<td>3.931</td>
<td>0.238</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C12[2][A]</td>
<td>un3_cnt_cry_21_0/I0</td>
</tr>
<tr>
<td>4.448</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C12[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_21_0/SUM</td>
</tr>
<tr>
<td>4.680</td>
<td>0.232</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[1][B]</td>
<td>cnt_3_cZ[21]/I0</td>
</tr>
<tr>
<td>5.052</td>
<td>0.372</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C12[1][B]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[21]/F</td>
</tr>
<tr>
<td>5.052</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[21]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[1][B]</td>
<td>cnt_Z[21]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[21]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C12[1][B]</td>
<td>cnt_Z[21]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.889, 52.510%; route: 0.471, 27.801%; tC2Q: 0.333, 19.689%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.813</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.173</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[2][B]</td>
<td>cnt_Z[24]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R13C13[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[24]/Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C13[0][B]</td>
<td>un3_cnt_s_24_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C13[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_s_24_0/SUM</td>
</tr>
<tr>
<td>4.449</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C13[2][B]</td>
<td>cnt_3_cZ[24]/I0</td>
</tr>
<tr>
<td>5.173</td>
<td>0.724</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R13C13[2][B]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[24]/F</td>
</tr>
<tr>
<td>5.173</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[24]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[2][B]</td>
<td>cnt_Z[24]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C13[2][B]</td>
<td>cnt_Z[24]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.241, 68.443%; route: 0.239, 13.174%; tC2Q: 0.333, 18.384%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.833</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.207</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.374</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_ssd1306_0_Z</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/Q</td>
</tr>
<tr>
<td>3.959</td>
<td>0.266</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I3</td>
</tr>
<tr>
<td>4.344</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>5.207</td>
<td>0.863</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C14[0][A]</td>
<td style=" font-weight:bold;">clk_ssd1306_0_Z/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C14[0][A]</td>
<td>clk_ssd1306_0_Z/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>clk_ssd1306_0_Z</td>
</tr>
<tr>
<td>3.374</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C14[0][A]</td>
<td>clk_ssd1306_0_Z</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.385, 20.837%; route: 1.129, 61.122%; tC2Q: 0.333, 18.041%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.873</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.233</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[20]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[20]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[1][A]</td>
<td>cnt_Z[20]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R12C12[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[20]/Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C12[1][B]</td>
<td>un3_cnt_cry_20_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C12[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_20_0/SUM</td>
</tr>
<tr>
<td>4.677</td>
<td>0.232</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[1][A]</td>
<td>cnt_3_cZ[20]/I0</td>
</tr>
<tr>
<td>5.233</td>
<td>0.556</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R12C12[1][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[20]/F</td>
</tr>
<tr>
<td>5.233</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[20]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[1][A]</td>
<td>cnt_Z[20]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[20]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C12[1][A]</td>
<td>cnt_Z[20]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.073, 57.281%; route: 0.467, 24.924%; tC2Q: 0.333, 17.795%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.873</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.233</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[22]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[22]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C12[0][A]</td>
<td>cnt_Z[22]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R14C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[22]/Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R13C12[2][B]</td>
<td>un3_cnt_cry_22_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R13C12[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_22_0/SUM</td>
</tr>
<tr>
<td>4.677</td>
<td>0.232</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C12[0][A]</td>
<td>cnt_3_cZ[22]/I0</td>
</tr>
<tr>
<td>5.233</td>
<td>0.556</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R14C12[0][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[22]/F</td>
</tr>
<tr>
<td>5.233</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[22]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C12[0][A]</td>
<td>cnt_Z[22]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[22]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R14C12[0][A]</td>
<td>cnt_Z[22]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.073, 57.281%; route: 0.467, 24.924%; tC2Q: 0.333, 17.795%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.988</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.347</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[13]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/Q</td>
</tr>
<tr>
<td>3.959</td>
<td>0.266</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I3</td>
</tr>
<tr>
<td>4.344</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>4.621</td>
<td>0.278</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[1][A]</td>
<td>cnt_3_cZ[13]/I1</td>
</tr>
<tr>
<td>5.347</td>
<td>0.726</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C13[1][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[13]/F</td>
</tr>
<tr>
<td>5.347</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[13]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[1][A]</td>
<td>cnt_Z[13]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[13]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C13[1][A]</td>
<td>cnt_Z[13]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.111, 55.884%; route: 0.544, 27.349%; tC2Q: 0.333, 16.767%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.988</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.347</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[14]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/Q</td>
</tr>
<tr>
<td>3.959</td>
<td>0.266</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I3</td>
</tr>
<tr>
<td>4.344</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>4.621</td>
<td>0.278</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[2][A]</td>
<td>cnt_3_cZ[14]/I1</td>
</tr>
<tr>
<td>5.347</td>
<td>0.726</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C13[2][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[14]/F</td>
</tr>
<tr>
<td>5.347</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[14]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[2][A]</td>
<td>cnt_Z[14]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[14]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C13[2][A]</td>
<td>cnt_Z[14]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.111, 55.884%; route: 0.544, 27.349%; tC2Q: 0.333, 16.767%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.075</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.434</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[0][B]</td>
<td>cnt_Z[19]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R12C12[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[19]/Q</td>
</tr>
<tr>
<td>3.959</td>
<td>0.266</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R13C12[1][A]</td>
<td>un3_cnt_cry_19_0/I0</td>
</tr>
<tr>
<td>4.476</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R13C12[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_19_0/SUM</td>
</tr>
<tr>
<td>4.708</td>
<td>0.232</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C12[0][B]</td>
<td>cnt_3_cZ[19]/I0</td>
</tr>
<tr>
<td>5.434</td>
<td>0.726</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R12C12[0][B]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[19]/F</td>
</tr>
<tr>
<td>5.434</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[19]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[0][B]</td>
<td>cnt_Z[19]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C12[0][B]</td>
<td>cnt_Z[19]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.243, 59.908%; route: 0.499, 24.027%; tC2Q: 0.333, 16.065%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.290</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.649</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[12]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/Q</td>
</tr>
<tr>
<td>3.959</td>
<td>0.266</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I3</td>
</tr>
<tr>
<td>4.344</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>4.923</td>
<td>0.579</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C13[0][B]</td>
<td>cnt_3_cZ[12]/I1</td>
</tr>
<tr>
<td>5.649</td>
<td>0.726</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C13[0][B]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[12]/F</td>
</tr>
<tr>
<td>5.649</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C13[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[12]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C13[0][B]</td>
<td>cnt_Z[12]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[12]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C13[0][B]</td>
<td>cnt_Z[12]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.111, 48.521%; route: 0.845, 36.922%; tC2Q: 0.333, 14.558%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.290</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.649</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[11]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/Q</td>
</tr>
<tr>
<td>3.959</td>
<td>0.266</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I3</td>
</tr>
<tr>
<td>4.344</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>4.923</td>
<td>0.579</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C13[0][A]</td>
<td>cnt_3_cZ[11]/I1</td>
</tr>
<tr>
<td>5.649</td>
<td>0.726</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C13[0][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[11]/F</td>
</tr>
<tr>
<td>5.649</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[11]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C13[0][A]</td>
<td>cnt_Z[11]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[11]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C13[0][A]</td>
<td>cnt_Z[11]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.111, 48.521%; route: 0.845, 36.922%; tC2Q: 0.333, 14.558%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.298</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.657</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[16]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R13C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/Q</td>
</tr>
<tr>
<td>3.959</td>
<td>0.266</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[3][B]</td>
<td>clk_ssd13063_cZ/I3</td>
</tr>
<tr>
<td>4.344</td>
<td>0.385</td>
<td>tINS</td>
<td>RR</td>
<td>13</td>
<td>R13C11[3][B]</td>
<td style=" background: #97FFFF;">clk_ssd13063_cZ/F</td>
</tr>
<tr>
<td>4.933</td>
<td>0.590</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[2][B]</td>
<td>cnt_3_cZ[16]/I1</td>
</tr>
<tr>
<td>5.657</td>
<td>0.724</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R12C12[2][B]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[16]/F</td>
</tr>
<tr>
<td>5.657</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[16]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C12[2][B]</td>
<td>cnt_Z[16]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[16]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C12[2][B]</td>
<td>cnt_Z[16]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.109, 48.256%; route: 0.856, 37.240%; tC2Q: 0.333, 14.504%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[21]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[21]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[21]/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[23]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[23]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[23]/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[16]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[16]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[16]/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[9]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[9]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[9]/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[8]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[8]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[8]/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[15]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[15]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[15]/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[7]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[7]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[7]/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>clk_ssd1306_0_Z</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>clk_ssd1306_0_Z/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>clk_ssd1306_0_Z/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[6]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[6]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[6]/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[5]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[5]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[5]/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>74</td>
<td>clk_ssd1306</td>
<td>8.307</td>
<td>4.268</td>
</tr>
<tr>
<td>26</td>
<td>clk_50M_c</td>
<td>2.178</td>
<td>3.796</td>
</tr>
<tr>
<td>13</td>
<td>clk_ssd13063</td>
<td>2.178</td>
<td>1.333</td>
</tr>
<tr>
<td>2</td>
<td>cnt[9]</td>
<td>3.659</td>
<td>0.339</td>
</tr>
<tr>
<td>2</td>
<td>cnt[10]</td>
<td>3.450</td>
<td>0.807</td>
</tr>
<tr>
<td>2</td>
<td>cnt[7]</td>
<td>3.689</td>
<td>0.345</td>
</tr>
<tr>
<td>2</td>
<td>cnt[8]</td>
<td>4.095</td>
<td>0.339</td>
</tr>
<tr>
<td>2</td>
<td>cnt[6]</td>
<td>2.886</td>
<td>1.142</td>
</tr>
<tr>
<td>2</td>
<td>cnt[5]</td>
<td>2.178</td>
<td>0.420</td>
</tr>
<tr>
<td>2</td>
<td>cnt[3]</td>
<td>2.320</td>
<td>0.345</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R9C12</td>
<td>0.458</td>
</tr>
<tr>
<td>R11C11</td>
<td>0.306</td>
</tr>
<tr>
<td>R13C12</td>
<td>0.292</td>
</tr>
<tr>
<td>R12C10</td>
<td>0.292</td>
</tr>
<tr>
<td>R8C16</td>
<td>0.278</td>
</tr>
<tr>
<td>R7C11</td>
<td>0.264</td>
</tr>
<tr>
<td>R11C10</td>
<td>0.236</td>
</tr>
<tr>
<td>R13C10</td>
<td>0.222</td>
</tr>
<tr>
<td>R12C9</td>
<td>0.222</td>
</tr>
<tr>
<td>R9C13</td>
<td>0.208</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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